DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1011

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Figure 1–17. MegaWizard Plug-In Manager—ALTGX (PCIe 2 Screen)
Table 1–17. MegaWizard Plug-In Manager Options (PCIe 2 Screen) (Part 1 of 2)
February 2011 Altera Corporation
Create a pipestatus output port
for PIPE interface status signal.
Create a pipedatavalid output
port to indicate valid data from the
receiver.
ALTGX Setting
Figure 1–17
Manager.
Table 1–17
Manager for your ALTGX custom megafunction variation.
lists the available options on the PCIe 2 screen of the MegaWizard Plug-In
shows the PCIe 2 screen of Protocol Settings for the MegaWizard Plug-In
The PCIe interface block receives status signals
from the transceiver channel PCS and PMA blocks
and encodes the status on a 3-bit output signal
(pipestatus[2:0]) that is forwarded to the FPGA
fabric.
This is an output status port that indicates the
receiver parallel data on the rx_dataout port is
valid.
Description
Stratix IV Device Handbook Volume 3
“Receiver Status” section and
Table 1-53 in the
Architecture in Stratix IV
Devices
chapter.
Reference
—
Transceiver
1–53