DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1131
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1131 of 1154
- Download datasheet (32Mb)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices—Preliminary
of 3)
April 2011 Altera Corporation
M144K
Block
Notes to
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50%
(2) This is only applicable to the Stratix IV E and GX devices.
(3) When you use the error detection CRC feature, there is no degradation in F
Memory
(3)
output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
Table
Single-port
2K×72
Simple dual-port
2K×72
Simple dual-port
2K×72, with the
read-during-write
option set to Old
Data
Simple dual-port
2K×64 (with ECC)
True dual-port
4K×36
True dual-port
4K×36, with the
read-during-write
option set to Old
Data
ROM 1 Port
ROM 2 Port
Min Pulse Width
(clock high time)
Min Pulse Width
(clock low time)
1–36:
1
Mode
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
ALUTs
Resources Used
—
—
0
0
0
0
0
0
0
0
TriMatrix
Memory
—
—
1
1
1
1
1
1
1
1
Commercial/
Speed Grade
Industrial
–2 /–2×
475
465
260
335
400
245
540
500
700
500
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
MAX
Commercial/
Speed Grade
Industrial
.
440
435
240
300
375
230
500
465
755
625
–3
Commercial/
Speed Grade
Industrial
Performance
380
385
205
255
330
205
435
400
860
690
–4
–3 Industrial
Speed Grade
400
375
225
295
350
225
450
425
860
690
(2)
(Note 1)
–4 Industrial
Speed Grade
(Part 3
350
325
200
250
310
200
420
400
950
690
(2)
1–49
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
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