DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 599

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
PCS code groups are sent via PCS ordered sets. PCS ordered sets consist of
combinations of special and data code groups defined as a column of code groups.
These ordered sets are composed of four code groups beginning in lane 0.
lists the defined idle ordered sets (||I||) that are used for the self-managed
properties of XAUI.
Table 1–59. Defined Idle Ordered Set
Stratix IV GX and GT transceivers configured in XAUI mode provide the following
protocol features:
■
■
■
■
■
■
XGMII-to-PCS code conversion at the transmitter
PCS-to-XGMII code conversion at the receiver
8B/10B encoding and decoding
IEEE P802.3ae-compliant synchronization state machine
±100 PPM clock rate compensation
Channel deskew of four lanes of the XAUI link
Code
||R||
||K||
||A||
||I||
Synchronization column
Align column
Skip column
Ordered Set
Idle
Code Groups
Number of
4
4
4
Stratix IV Device Handbook Volume 2: Transceivers
/K28.5/K28.5/K28.5/K28.5/
/K28.0/K28.0/K28.0/K28.0/
/K28.3/K28.3/K28.3/K28.3/
Substitute for XGMII Idle
Encoding
Table 1–59
1–155