DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 841

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: Reset Control and Power Down in Stratix IV Devices
PMA Direct Drive Mode Reset Sequences
February 2011 Altera Corporation
As shown in
Direct) drive double-width configuration, non-bonded with CDR in manual lock
mode, follow these reset steps:
1. After power up, assert pll_powerdown of each channel for a minimum period of
2. Keep the rx_analogreset and rx_locktorefclk signals of each channel asserted
3. When the transmitter PLL locks, as indicated by the pll_locked signal going high
4. For the receiver operation, after de-assertion of the busy signal (marker 4), wait for
5. Wait for the rx_pll_locked signal from each channel to go high. The
6. In a Basic (PMA Direct) drive double-width configuration without bonding
7. After assertion of the rx_locktodata signal, from that point onwards, wait for at
t
and the rx_locktodata signals de-asserted during this time period. After you
de-assert the pll_powerdown signal, the transmitter PLL starts locking to the
transmitter input reference clock.
(marker 3), the transmitters are ready to accept parallel data from the FPGA fabric
and subsequently transmitting serial data reliably.
a minimum of two parallel clock cycles to de-assert the rx_analogreset signal of
each channel. After the rx_analogreset signal is de-asserted, the receiver CDR of
each channel starts locking to the receiver input reference clock because
rx_locktorefclk is asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at marker 6).
between channels, when the rx_pll_locked signal of all the channels has gone
high, from that point onwards, wait for at least t
rx_locktorefclk and assert rx_locktodata (marker 7). At this point, the receiver
CDR of all the channels enters into lock-to-data mode and starts locking to the
received data.
least t
point, all the receivers are ready for transferring valid parallel data into the FPGA
fabric (until this time, Altera recommends that the user logic that processes this
data be reset).
pll_powerdown
LTD_M anual
Figure
(the time between markers 1 and 2).
4–19, for the receiver and transmitter channel in Basic (PMA
(marker 8) for the receiver parallel clock to be stable. At this
Stratix IV Device Handbook Volume 2: Transceivers
LTR_LTD_Manual
, then de-assert
4–35