DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 928

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–82
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 7 of 13)
Stratix IV Device Handbook Volume 2: Transceivers
tx_preemp_0t[4:0]
tx_preemp_1t[4:0]
Port Name
(1)
(1)
Output
Input/
Input
Input
This is an optional pre-emphasis control for pre-tap for the transmit
buffer. Depending on what value you set at this input, the controller
dynamically writes the value to the pre-emphasis control register of
the transmit buffer. This signal controls both pre-emphasis positive
and its inversion.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page
The following values are the legal settings allowed for this signal:
0 represents 0
1-15 represents -15 to -1
16 represents 0
17 - 31 represents 1 to 15
In the PCIe configuration, set tx_preemp_0t[4:0] to 5'b00000
when you do a rate switch from Gen 1 mode to Gen 2 mode. This is
to ensure that tx_preemp_0t[4:0] does not add to the signal
boost when tx_pipemargin and tx_pipedeemph take affect in
PCIe Gen 2 mode.
For more information, refer to the “Programmable Pre-Emphasis”
section of the
This is an optional pre-emphasis write control for the first post-tap
for the transmit buffer. Depending on what value you set at this
input, the controller dynamically writes the value to the first
post-tap control register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page 5–13
section of the
Transceiver Architecture in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
5–13.
and the “Programmable Pre-Emphasis”
Description
Dynamic Reconfiguration Controller Port List
“Dynamically Reconfiguring PMA
“Dynamically Reconfiguring PMA
February 2011 Altera Corporation
(Note
3),
chapter.
chapter.
(4)