DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 74

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–18
Stratix IV Device Handbook Volume 1
Conflict Resolution
Read-During-Write Behavior
f
MLABs can implement single-port SRAM through emulation using the Quartus II
software. Emulation results in minimal additional logic resources being used. Because
of the dual-purpose architecture of the MLAB, it only has data input registers and
output registers in the block. MLABs gain input address registers and additional data
output registers from ALMs.
For more information about register packing, refer to the
Adaptive Logic Modules in Stratix IV Devices
When using memory blocks in true dual-port mode, it is possible to attempt two write
operations to the same memory location (address). Because no conflict resolution
circuitry is built into the memory blocks, this results in unknown data being written to
that location. Therefore, you must implement conflict resolution logic external to the
memory block to avoid address conflicts.
You can customize the read-during-write behavior of the Stratix IV TriMatrix memory
blocks to suit your design needs. Two types of read-during-write operations are
available: same port and mixed port.
two types.
Figure 3–15. Stratix IV Read-During-Write Data Flow
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true dual-port
RAM. For MLABs, the output of the MLABs can only be set to don’t care in same-port
read-during-write mode. In this mode, the output of the MLABs is unknown during a
write cycle. There is a window near the falling edge of the clock during which the
output is unknown. Prior to that window, “old data” is read out; after that window,
“new data” is seen at the output.
Port A
data in
Port A
data out
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Figure 3–15
chapter.
shows the difference between the
Port B
data in
Port B
data out
Logic Array Blocks and
February 2011 Altera Corporation
Design Considerations
Mixed-port
data flow
Same-port
data flow