DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 623

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–145. SDI Mode
Note to
(1) Not supported in Stratix IV GT devices.
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
PMA-PCS Interface
Interface Frequency
Fabric-Transceiver
Functional Modes
Low-Latency PCS
Encoder/Decoder
Fabric-Transceiver
Rate Match FIFO
Data Rate (Gbps)
(Pattern Length)
Channel Bonding
Functional Mode
TX PCS Latency
Interface Frequency
RX PCS Latency
Figure
Byte Ordering
Interface Width
Word Aligner
Byte SerDes
8B/10B
FPGA
FPGA
(MHz)
Width
1–45:
Figure 1–145
devices.
8-bit
Single
Width
10-bit
Basic
shows SDI mode configurations supported in Stratix IV GX and GT
Disabled
Disabled
148.35
16-bit
10-Bit
148.5/
9 - 11
5 - 6
(1.485/1.4835) (1)
Double
Width
Disabled
Stratix IV GX and GT Configurations
Disabled
HD-SDI
Disabled
Bit-Slip
20-bit
x1
Disabled
Enabled
74.175
74.25/
20-Bit
4 - 5.5
6 - 8
10-bit
PIPE
10-bit
XAUI
SDI
GIGE
10-bit
Protocol
SRIO
10-bit
Stratix IV Device Handbook Volume 2: Transceivers
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
(2.97/2.967)
Disabled
Disabled
Disabled
Disabled
Enabled
148.5/
148.35
3G-SDI
Bit-Slip
20-bit
4 - 5.5
x1
6 - 8
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
1–179