DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 360

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

10–26
Stratix IV Device Handbook Volume 1
PS Configuration Using a MAX II Device as an External Host
1
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix IV device. You can store configuration data in .rbf, .hex,
or .ttf format.
Figure 10–10
device and a MAX II device for single device configuration.
Figure 10–10. Single Device PS Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix IV device. V
After power-up, Stratix IV devices go through a POR. The POR delay depends on the
PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T
4 ms < T
all user I/O pins. After the device successfully exits POR, all user I/O pins continue to
be tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors that are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages—reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset. To initiate
configuration, the MAX II device must generate a low-to-high transition on the
nCONFIG pin.
V
be fully powered to the appropriate voltage levels to begin the configuration process.
CC
high enough to meet the V
up all configuration system I/Os with V
, V
Figure
CCIO
POR
(MAX II Device or
, V
Microprocessor)
POR
10–10:
External Host
< 12 ms. During POR, the device resets, holds nSTATUS low, and tri-states
ADDR
shows the configuration interface connections between a Stratix IV
CCPGM
< 300 ms. When PORSEL is driven high, the fast POR time is
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Memory
, and V
DATA0
IH
specification of the I/O on the device and the external host. Altera recommends powering
CCPD
CCPGM
of the banks where the configuration pins reside must
V
10 k Ω
CCPGM (1)
.
10 k Ω
V
CCPGM (1)
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix IV Device
MSEL2
MSEL1
MSEL0
nCEO
April 2011 Altera Corporation
Passive Serial Configuration
N.C.
GND
V
CCPGM
CCPGM
must be