DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 794

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–40
Stratix IV Device Handbook Volume 2: Transceivers
In this case, the ATX PLL provides the high-speed clock to the transmitter channel of
inst1. Therefore, you can combine 10 channels of inst0 and one channel of inst1 in
two transceiver blocks, as shown in
Figure 3–21. Combining Basic (PMA Direct) ×N Configuration with Non-Basic (PMA Direct)
Configuration Using an ATX PLL for Example 10
Notes to
(1) The ATX PLL provides the high-speed clock to channel 0 of inst1.
(2) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents
the ×N bottom clock line.
Figure
3–21:
Base data rate
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
ATX PLL
5 Gbps
CMU0
CMU0 Channel
PLL
RX
RX
RX
RX
RX
Inst0: Channel 0
RX
RX
RX
RX
RX
ATX PLL block
Inst0: Channel 4
RX
Inst0: Channel 1
Inst0: Channel 2
Inst0: Channel 5
Inst0: Channel 8
Inst0: Channel 3
Inst0: Channel 6
Inst0: Channel 7
Inst0: Channel 9
Inst1: Channel 0
GXBR0
GXBR1
Combining Transceiver Channels in Basic (PMA Direct) Configurations
Figure
TX
TX
TX
TX
TX
Central
Divider
TX
TX
TX
TX
TX
Clock
TX
Central
Divider
Clock
(Note 1)
3–21.
x4 Clock Line (2)
xN Bottom Clock Line (2)
xN Top Clock Line (2)
February 2011 Altera Corporation