DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 656

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–212
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 1 of 7)
Stratix IV Device Handbook Volume 2: Transceivers
rx_syncstatus
rx_bitslip
rx_ala2size
rx_rlv
Port Name
Table 1–74
Output
Output
Output
Input/
Input
Input
lists the ALTGX megafunction receiver ports.
pulse width is two
pulse width is two
a minimum of two
minimum of three
Signal. Minimum
signal. Driven for
signal. Minimum
coreclkout for
Synchronous to
recovered clock
recovered clock
rx_clkout or
rx_clkout for
bonded modes
serializer and a
Asynchronous
Asynchronous
Asynchronous
configurations
configurations
Clock Domain
coreclkout.
parallel clock
parallel clock
without byte
non-bonded
serializer.
with byte
cycles in
cycles in
modes.
cycles.
cycles.
Word alignment synchronization status
indicator.
■
■
■
For more information, refer to
Single-Width Mode” on page 1–60
Aligner in Double-Width Mode” on page
■
Bit-slip control for the word aligner configured
in bit-slip mode.
At every rising edge, word aligner slips one bit
into the received data stream, effectively
shifting the word boundary by one bit.
Available only in SONET OC-12 and OC-48
modes. Select between these options:
■
■
Run-length violation indicator.
A high pulse is driven when the number of
consecutive 1s or 0s in the received data
stream exceeds the programmed run length
violation threshold.
Automatic synchronization state machine
mode—this signal is driven high if the
conditions required to remain in
synchronization are met. Driven low if the
conditions required to lose synchronization
are met.
Manual alignment mode—the behavior of
this signal depends on whether the
transceiver is configured in single-width or
double-width mode.
Bit-Slip mode—not available.
Channel width:
8/10—rx_syncstatus = 1
16/20—rx_syncstatus = 2 32/40—
rx_syncstatus = 4
0 = 16-bit A1A2
1 = 32-bit A1A1A2A2
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
“Word Aligner in
and
“Word
Transceiver Port Lists
1–66.
Channel
Channel
Channel
Channel
Scope