DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 330

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

9–2
Stratix IV Device Handbook Volume 1
Stratix IV Devices can be Driven Before Power Up
I/O Pins Remain Tri-Stated During Power Up
Insertion or Removal of a Stratix IV Device from a Powered-Up System
1
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of
Stratix IV devices before or during power up or power down without damaging the
device.
A device that does not support hot socketing can interrupt system operation or cause
contention by driving out before or during power up. In a hot-socketing situation, the
Stratix IV device’s output buffers are turned off during system power up or power
down. Also, the Stratix IV device does not drive out until the device is configured and
working within the recommended operating conditions.
Devices that do not support hot socketing can short power supplies when powered
up through the device signal pins. This irregular power up can damage both the
driving and driven devices and can disrupt card power up.
You can insert a Stratix IV device into or remove it from a powered-up system board
without damaging the system board or interfering with its operation.
You can power up or power down the V
sequence (with any time between them) which are monitored by the hot socket circuit.
In addition, all other power supplies for the device can be powered up or down in any
sequence. Individual power supply ramp-up and ramp-down rates range from 50 µs
to 100 ms. During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
To successfully power-up and exit POR on production devices, fully power V
before V
A possible concern regarding hot socketing is the potential for “latch-up.” Stratix IV
devices are immune to latch-up when hot socketing. Latch-up can occur when
electrical subsystems are hot socketed into an active system. During hot socketing, the
signal pins can be connected and driven by the active system before the power supply
can provide current to the device’s power and ground planes. This condition can lead
to latch-up and cause a low-impedance path from power to ground within the device.
As a result, the device draws a large amount of current, possibly causing electrical
damage.
CCAUX
begins to ramp.
Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
CCIO
, V
CC
, V
CCPGM
, and V
Stratix IV Hot-Socketing Specifications
February 2011 Altera Corporation
CCPD
supplies in any
CC