DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 119

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–1. GCLK Networks
February 2011 Altera Corporation
Global Clock Networks
Stratix IV devices provide up to 16 GCLKs that can drive throughout the device,
serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks,
and PLLs. Stratix IV device I/O elements (IOEs) and internal logic can also drive
GCLKs to create internally generated global clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–1
Stratix IV devices.
CLK[0..3]
shows the CLK pins and PLLs that can drive the GCLK networks in
L1
L2
L3
L4
GCLK[0..3]
GCLK[12..15]
GCLK[4..7]
CLK[12..15]
CLK[4..7]
T1 T2
B1 B2
GCLK[8..11]
R1
R2
R3
R4
CLK[8..11]
Stratix IV Device Handbook Volume 1
5–3