DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 694

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–22
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel Datapath Clocking Resources
The Stratix IV transceivers support various non-bonded and bonded transceiver
clocking configurations through the dedicated ×1, ×4, and ×N high-speed serial and
low-speed parallel clock lines.
Figure 2–13
modes.
Figure 2–13. Transceiver Clock Distribution in the Stratix IV GT EP4S100G5F45 and Stratix IV GX
EP4SGX530KF40 Devices
Note to
(1) The 10G ATX PLL block is not available for the EP4SGX530KF40 device.
Table
2–14:
shows the transceiver clock distribution in ×1, ×4, ×8, and ×N bonded
Transceiver Block GXBR2
Transceiver Block GXBR3
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL Block (10G) (1)
ATX PLL Block (6G)
ATX PLL Block (6G)
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
Channel 1
Channel 0
Channel 3
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 2
Channel 3
Channel 2
CMU1 GXBR2
CMU1 GXBR3
CMU1 GXBR1
CMU1 GXBR0
x1
x1
x1
x1
CMU0 GXBR3
CMU0 GXBR0
CMU0 GXBR1
CMU0 GXBR2
x1
x1
x1
x1
x4 GXBR3
x4 GXBR2
x4 GXBR1
Chapter 2: Transceiver Clocking in Stratix IV Devices
x4 GXBR0
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Transceiver Channel Datapath Clocking
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February 2011 Altera Corporation