DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 933

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 12 of 13)
February 2011 Altera Corporation
reconfig_reset
aeq_fromgxb[7:0]
aeq_togxb
ctrl_address[15:0]
ctrl_writedata[15:0]
ctrl_readdata[15:0]
ctrl_write
ctrl_read
Port Name
Output
Output
Output
Input/
Input
Input
Input
Input
Input
Input
This is an optional signal that you can use to reset the
ALTGX_RECONFIG instance. reconfig_reset must be held high
for at least one clock cycle to take effect.
The width of this signal depends on the number of channels
controlled by the ALTGX_RECONFIG instance. For example, if you
select the total number of channels controlled by the
ALTGX_RECONFIG instance as follows:
1 ≤ Channels ≤ 4, then the input port reconfig_fromgxb = 8 bits
5 ≤ Channels ≤ 8, then the input port reconfig_fromgxb =
16 bits
9 ≤ Channels ≤ 12, then the input port reconfig_fromgxb =
24 bits
This signal is available only when you enable the AEQ control
option. You must connect this signal between the
ALTGX_RECONFIG and ALTGX instances when using AEQ control.
The width of this signal depends on the number of channels
controlled by the ALTGX_RECONFIG instance. For example, if you
select the total number of channels controlled by the
ALTGX_RECONFIG instance as follows:
1 ≤ Channels ≤ 4, then the input port reconfig_fromgxb =
24 bits
5 ≤ Channels ≤ 8, then the input port reconfig_fromgxb =
48 bits
9 ≤ Channels ≤ 12, then the input port reconfig_fromgxb =
64 bits
This signal is available only when you enable the AEQ control
option. You must connect this signal between the
ALTGX_RECONFIG and ALTGX instances when using AEQ control.
Used for EyeQ control. This port is used to specify the address of
the EyeQ interface register for read and write operations.
Used for EyeQ control. Data present on this port is written to the
EyeQ interface register selected using the ctrl_address port.
Used for EyeQ control. Contents of the EyeQ interface register
selected using the ctrl_address port are available on this port
after a read operation.
Used for EyeQ control. Assert this signal high to write the data
present on the ctrl_writedata port to the EyeQ interface
registers.
Used for EyeQ control. Assert this signal high to read the contents
of the EyeQ interface registers to the ctrl_readdata port.
Stratix IV Device Handbook Volume 2: Transceivers
Description
(Note
3),
(4)
5–87