DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 54

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

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Stratix IV Device Handbook Volume 1
ALM Interconnects
Clear and Preset Logic Control
There are three dedicated paths between the ALMs—register cascade, carry chain,
and shared arithmetic chain. Stratix IV devices include an enhanced interconnect
structure in LABs for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB for fast shift
registers. These ALM-to-ALM connections bypass the local interconnect. The
Quartus II Compiler automatically takes advantage of these resources to improve
utilization and performance.
chain, and register chain interconnects.
Figure 2–15. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects
LAB-wide signals control the logic for the register ’s clear signal. The ALM directly
supports an asynchronous clear function. You can achieve the register preset through
the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to
two clears.
Stratix IV devices provide a device-wide reset pin (DEV_CLRn) that resets all the
registers in the device. An option set before compilation in the Quartus II software
controls this pin. This device-wide reset overrides all other control signals.
routing to adjacent ALM
Carry chain & shared
arithmetic chain
interconnect
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Figure 2–15
Local
Local interconnect
routing among ALMs
in the LAB
shows the shared arithmetic chain, carry
ALM 10
ALM 1
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
ALM 9
Register chain
routing to adjacent
ALM's register input
February 2011 Altera Corporation
Adaptive Logic Modules