DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 89

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
Stratix IV DSP Block Resource Descriptions
Figure 4–6. Half DSP Block Architecture
Notes to
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) The chainin port must only be connected to chainout of the previous DSP blocks and must not be connected to general routings.
February 2011 Altera Corporation
datab_2[ ]
datab_3[ ]
datab_1[ ]
dataa_2[ ]
dataa_3[ ]
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
Figure
chainin[ ] (3)
scanina[ ]
4–6:
loopback
scanouta
The DSP block consists of the following elements:
■
■
■
■
■
■
Figure 4–6
Table 4–9 on page 4–34
clock[3..0]
ena[3..0]
alcr[3..0]
Input register bank
Four two-multiplier adders
Pipeline register bank
Two second-stage adders
Four rounding and saturation logic units
Second adder register and output register bank
Half-DSP Block
shows a detailed overall architecture of the top half of the DSP block.
chainout_saturate
chainout_round
zero_loopback
zero_chainout
accum_sload
shows a list of DSP block dynamic signals.
output_saturate
output_round
shift_right
rotate
signa
signb
chainout
Stratix IV Device Handbook Volume 1
overflow (1)
chainout_sat_overflow (2)
result[ ]
4–9