DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 242
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 242 of 1154
- Download datasheet (32Mb)
7–22
Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
Stratix IV Device Handbook Volume 1
(2), (3),
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
(4)
I/O Bank 1B
36 User I/Os
50 User I/Os
I/O Bank 2B
I/O Bank 1C
I/O Bank 2C
36 User I/Os
I/O Bank 1A
50 User I/Os
I/O Bank 2A
7–17:
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x4=6
x4=7
DLL1
x4=6
x4=7
DLL0
x4=7
x4=7
I/O Bank 8A
I/O Bank 3A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 3C
I/O Bank 8C
48 User I/Os
48 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
in the 1760-Pin FineLine BGA
x8/x9=3
x4=6
x4=6
EP4SE820 Devices
UP
and R
DN
I/O Bank 7C
48 User I/Os
I/O Bank 4C
48 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=6
x4=6
Chapter 7: External Memory Interfaces in Stratix IV Devices
I/O Bank 7B
I/O Bank 4B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 7A
I/O Bank 4A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
February 2011 Altera Corporation
Memory Interfaces Pin Support
DN
pins for OCT calibration, you
I/O Bank 6C
50 User I/Os
50 User I/Os
I/O Bank 5C
36 User I/Os
x16/x18=1
x32/x36=0
I/O Bank 5A
50 User I/Os
I/O Bank 6B
36 User I/Os
I/O Bank 5B
I/O Bank 6A
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x4=7
x4=7
x4=6
x4=7
DLL2
x4=6
DLL3
x4=7
(Note
1),
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