DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 850

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–4
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic
Reconfiguration
Stratix IV Device Handbook Volume 2: Transceivers
ALTGX MegaWizard Plug-In Manager
f
1
Stratix IV GX devices provide two MegaWizard Plug-In Manager interfaces to
support dynamic reconfiguration—ALTGX and ALTGX_RECONFIG.
Use the ALTGX MegaWizard Plug-In manager to enable the dynamic reconfiguration
settings for the transceiver instances.
For more information, refer to the “Reconfiguration Settings” section of the
Transceiver Setup Guide for Stratix IV Devices
The reconfig_clk Clock Requirements for the ALTGX Instance
You must connect the reconfig_clk port to the ALTGX instance in all the
configurations using the dynamic reconfiguration feature.
Table 5–2
instance, based on its configuration.
Table 5–2. Source Clock for the Offset Cancellation Circuit in the ALTGX Instance
Select the reconfig_clk frequency based on the ALTGX configuration shown in
Table
not use dedicated transceiver REFCLK pins or any clocks generated by transceivers.
Altera recommends driving the reconfig_clk signal on a global clock resource. This
clock must be a free-running clock sourced from an I/O clock pin. Do not use
dedicated transceiver refclk pins or any clocks generated by transceivers.
Table 5–3. reconfig_clk Settings for the ALTGX Instance
Note to
(1) The clock source used for offset cancellation must be a free running clock that is not derived from the PLL as this
Note to
(1) The source clock for the offset cancellation circuit in the ALTGX instance must be faster than 37.5 MHz. Offset
Source Clock for the Offset Cancellation Circuit
clock is required for offset cancellation at power up.
cancellation is not required for transmitters and is accomplished using a fixed clock in PCIe mode.
5–3. This clock must be a free-running clock sourced from an I/O clock pin. Do
Figure
Figure
lists the source clock for the offset cancellation circuit in the ALTGX
ALTGX Instance Configuration
5–2:
5–3:
Transmitter only and PCIe
Receiver and Transmitter
reconfig_clk
reconfig_clk
Receiver only
fixedclk
Quartus II MegaWizard Plug-In Manager Interfaces to Support Dynamic Reconfiguration
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
chapter.
(1)
reconfig_clk Frequency Range (MHz)
Receiver only and Transmitter only
Receiver and Transmitter
ALTGX Configurations
PCI Express
February 2011 Altera Corporation
2.5
37.5 to 50
37.5 to 50
(1)
to 50
®
(PCIe)
ALTGX