DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 737

KIT DEVELOPMENT STRATIX IV

DK-DEV-4SGX230N

Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr

Specifications of DK-DEV-4SGX230N

Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-DEV-4SGX230N
Manufacturer:
ALTERA
0
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–34. FPGA Fabric-Receiver Interface Clocking for Non-Bonded Channel Configurations Without Rate Matcher
Note to
(1) The red lines represent rx_clkout[3], the blue lines represent rx_clkout[2], the green lines represent rx_clkout[1], and the brown lines
February 2011 Altera Corporation
(Note 1)
represent rx_clkout[0].
Figure
and Status
and Status
and Status
Channel 2
Channel 1
and Status
Channel 3
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
2–34:
rx_coreclk[2]
rx_coreclk[0]
rx_coreclk[1]
rx_coreclk[3]
Figure 2–34
channel configurations without rate matcher.
rx_clkout[1]
rx_clkout[0]
rx_clkout[2]
rx_clkout[3]
shows the FPGA fabric-Receiver interface clocking for non-bonded
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
/2
/2
/2
/2
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Parallel Recovered Clock
Parallel Recovered Clock
Parallel Recovered Clock
Parallel Recovered Clock
Stratix IV Device Handbook Volume 2: Transceivers
Channel 2
Channel 1
Channel 3
Channel 0
Receiver Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Receiver PMA
Receiver PMA
Receiver PMA
CDR
CDR
CDR
CDR
Input Reference Clock
rx_datain[2]
Input Reference Clock
rx_datain[3]
Input Reference Clock
rx_datain[1]
rx_datain[0]
2–65

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