DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 364

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

10–30
Figure 10–12. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V
(2) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
Stratix IV Device Handbook Volume 1
meet the V
(MAX II Device or
Figure
Microprocessor)
External Host
ADDR
IH
Memory
10–12:
specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V
f
1
DATA0
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth
device. Devices must be the same density and package. All devices start and complete
configuration at the same time.
Figure 10–12
receiving the same configuration data.
You can use a single configuration chain to configure Stratix IV devices with other
Altera devices. To ensure that all devices in the chain complete configuration at the
same time, or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
V
CCPGM (1)
10 k Ω
V
CCPGM (1)
shows multi-device PS configuration when both Stratix IV devices are
10 k Ω
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix IV Device
Configuring Mixed Altera FPGA Chains
MSEL2
MSEL1
MSEL0
nCEO
N.C.
GND
V
(2)
CCPGM
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix IV Device
CCPGM
STATUS
April 2011 Altera Corporation
MSEL2
MSEL1
MSEL0
Passive Serial Configuration
nCEO
must be high enough to
specification.
chapter in
N.C.
GND
(2)
V
CCPGM
CCPGM
.