DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 782

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–28
Stratix IV Device Handbook Volume 2: Transceivers
Figure 3–13
gxb_powerdown and pll_powerdown ports for channels 0 to 4 and channels 5 and 6 are
driven from the same logic.
Figure 3–13. Combined Channels After Compilation for Example 5
If you connect each of the seven bits of the gxb_powerdown and pll_powerdown ports to
different reset control logic, the Quartus II software requires seven transceiver blocks
to combine the seven channels in the instance.
shows the conditions after compilation. In this example, the
RX
Transceiver Block1
RX
RX
RX
RX
RX
RX
Transceiver Block0
Inst0: Channel 3
Inst0: Channel 2
Inst0: Channel 4
Inst0: Channel 5
Inst0: Channel 0
Inst0: Channel 1
Inst0: Channel 6
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
TX
TX
TX
TX
TX
TX
TX
Combining Transceiver Channels in Basic (PMA Direct) Configurations
CMU PLL
CMU PLL
February 2011 Altera Corporation