DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 296
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 296 of 1154
- Download datasheet (32Mb)
8–18
Figure 8–12. Receiver Block Diagram
Notes to
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Differential I/O Termination
8–12:
10
The Stratix IV device family provides a 100-Ω, on-chip differential termination option
on each differential receiver channel for LVDS standards. On-chip termination saves
board space by eliminating the need to add external resistors on the board. You can
enable on-chip termination in the Quartus II software Assignment Editor.
On-chip differential termination is supported on all row I/O pins and dedicated clock
input pins (CLK[0,2,9,11]). It is not supported for column I/O pins, dedicated clock
input pins (CLK[1,3,8,10]), or the corner PLL clock inputs.
Figure 8–13
Figure 8–13. On-Chip Differential I/O Termination
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows device on-chip termination.
(Note
IOE
2
Left/Right PLL
Transmitter
1),
LVDS
3
(2)
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
rx_outclk)
diffioclk
Z
Z
rx_inclock
0
0
= 50 Ω
= 50 Ω
8 Serial LVDS
Clock Phases
Synchronizer
Receiver with On-Chip
DOUT DIN
Stratix IV Differential
100 Ω Termination
R
D
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
February 2011 Altera Corporation
DPA Circuitry
DPA Clock
Retimed
Data
DIN
Differential Receiver
LVDS Clock Domain
DPA Clock Domain
+
rx_in
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