DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 706

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–34
Figure 2–20. Four PCIe ×8 Links in Eight Transceiver Block Devices
Note to
(1) You can use a ×4 PCIe configuration in either a master or slave block.
Stratix IV Device Handbook Volume 2: Transceivers
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
2–20:
f
Figure 2–20
Non-Bonded Basic (PMA Direct) Mode Channel Configurations
Figure 2–21
configured in non-bonded Basic (PMA Direct) mode. Each channel derives its clock
independently from either the CMU0 PLL or CMU1 PLL within the same transceiver
block if the CMU channel is configured as a CMU PLL.
For more information about Basic (PMA Direct) mode, refer to the
Architecture in Stratix IV Devices
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
GXBL0 (Master)
EP4SGX530NF45
GXBL2 (Master)
GXBL3 (Slave)
GXBL1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
shows four PCIe ×8 links in eight transceiver block devices.
shows four regular channels and the CMU1 channel in a transceiver block
Fourth PCIe
Third PCIe
x8 Link
x8 Link
chapter.
Second PCIe
First PCIe
x8 Link
x8 Link
(Note 1)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
GXBR0 (Master)
GXBR2 (Master)
GXBR3 (Slave)
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transceiver
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0