DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 127

DK-DEV-4SGX230N

Manufacturer Part Number

DK-DEV-4SGX230N

Description

KIT DEVELOPMENT STRATIX IV

Manufacturer

Altera

Series

Stratix® IVr

Type

FPGAr

Datasheets

1.EP4SGX110DF29C3N.pdf (80 pages)

2.EP4SGX110DF29C3N.pdf (1154 pages)

3.DK-DEV-4SGX230N.pdf (2 pages)

4.DK-DEV-4SGX530N.pdf (57 pages)

Specifications of DK-DEV-4SGX230N

Contents

Development Board, Universal Power Supply, Cables and Software

Silicon Manufacturer

Altera

Core Architecture

FPGA

Core Sub-architecture

Stratix

Silicon Core Number

EP4S

Silicon Family Name

Stratix IV GX

Rohs Compliant

Yes

For Use With/related Products

EP4SGX230K

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

544-2594

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

DK-DEV-4SGX230N

Manufacturer:

Altera

Quantity:

135

Company:

BOSTOCK HK LIMITED

Part Number:

DK-DEV-4SGX230N

Manufacturer:

ALTERA

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

Clock Networks in Stratix IV Devices

Table 5–2. Clock Input Pin Connectivity to the GCLK Networks

Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)

February 2011 Altera Corporation

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

GCLK8

GCLK9

GCLK10

GCLK11

GCLK12

GCLK13

GCLK14

GCLK15

RCLK [0, 4, 6, 10]

RCLK [1, 5, 7, 11]

RCLK [2, 8]

RCLK [3, 9]

RCLK [13, 17, 21, 23,

27, 31]

RCLK [12, 16, 20, 22,

26, 30]

RCLK [15, 19, 25, 29]

RCLK [14, 18, 24, 28]

RCLK [35, 41]

Clock Resources

Clock Resource

PLL Clock Outputs

Stratix IV PLLs can drive both GCLK and RCLK networks, as described in

on page 5–13

Table 5–2

Table 5–3

Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to

create a dual-regional clock network.

—

lists the connection between the dedicated clock input pins and GCLKs.

lists the connectivity between the dedicated clock input pins and RCLKs in

—

and

—

v —

Table 5–6 on page

—

v —

—

CLK (p/n Pins)

5–13.

—

CLK (p/n Pins)

—

Stratix IV Device Handbook Volume 1

—

Table 5–5

—

5–11

—

DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 127

DK-DEV-4SGX230N

Specifications of DK-DEV-4SGX230N

Available stocks

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