DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 152

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–36
Stratix IV Device Handbook Volume 1
Programmable Bandwidth
Stratix IV PLLs provide advanced control of the PLL bandwidth using the PLL loop’s
programmable characteristics, including loop filter and charge pump.
Background
PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. The closed-loop gain 3 dB frequency in the PLL determines PLL
bandwidth. Bandwidth is approximately the unity gain point for open loop PLL
response. As
frequency. Stratix IV PLLs provide three bandwidth settings—low, medium (default),
and high.
Figure 5–32. Open- and Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
Closed-Loop Reponse Bode Plot
Gain
Gain
0 dB
Figure 5–32
shows, these points correspond to approximately the same
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Frequency
Frequency
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
February 2011 Altera Corporation
PLLs in Stratix IV Devices