DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 699
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 699 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
1
Bonded Channel Configurations
In PCS and PMA bonded channel configurations, the PCS and PMA blocks of all
bonded channels are clocked by the same low-speed parallel clock and high-speed
serial clock from the CMU0 clock divider or the ATX PLL block. The phase
compensation FIFOs of all bonded channels also share common read and write
pointers and enable signals generated in the CCU.
Stratix IV devices support ×4 PCS and PMA channel bonding that allows bonding of
four channels within the same transceiver block. Stratix IV devices also support ×8
channel bonding that allows bonding of eight PCS and PMA channels across two
transceiver blocks on the same side of the device.
The following functional modes support ×4 PCS and PMA bonded transmitter
channel configuration:
■
■
■
Use the CMU channels to generate the transceiver clocks for all ×4 bonded functional
modes listed above. Additionally, you may use the ATX PLLs to generate the
transceiver clocks for PCIe ×4 Gen 2 and Basic ×4 functional mode.
You must assign tx_dataout[0] of the ×4 bonded link (XAUI or PCIe ×4) to physical
channel 0 of the transceiver block, tx_dataout[1] to physical channel 1 of the
transceiver block, tx_dataout[2] to physical channel 2 of the transceiver block, and
tx_dataout[3] to physical channel 3 of the transceiver block. Otherwise, the
Quartus II compilation errors out.
PCIe ×4—Gen1 and Gen2
XAUI
Basic ×4
×4 PCS and PMA Bonded Channel Configuration
Stratix IV Device Handbook Volume 2: Transceivers
2–27
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: