DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 713
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 713 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–9. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes Without Rate Matcher
February 2011 Altera Corporation
SONET/SDH OC12
SONET/SDH OC48
HD-SDI
3G-SDI
Functional Mode
Depending on whether you use the byte deserializer or not, the parallel recovered
clock (when you do not use the byte deserializer) or a divide-by-two version of the
parallel recovered clock (when you use the byte deserializer) clocks the write port of
the receiver phase compensation FIFO. This clock is driven directly on the rx_clkout
port as the FPGA fabric-Transceiver interface clock. You can use the rx_clkout signal
to capture the receiver data and status signals in the FPGA fabric.
Table 2–9
modes without rate matcher.
Non-Bonded Receiver Clocking with Rate Matcher
The following functional modes have non-bonded receiver channel configuration
with rate-matcher:
■
■
■
■
1.4835 Gbps
2.488 Gbps
1.485 Gbps
2.967 Gbps
Data Rate
622 Mbps
2.97 Gbps
PCIe ×1
GIGE
Serial RapidIO
Basic with rate matcher
lists the receiver datapath clock frequencies in non-bonded functional
Serial Recovered
Clock Frequency
741.75 MHz
1.4835 GHz
742.5 MHz
1.244 GHz
1.485 GHz
311 MHz
Clock Frequency (MHz)
Parallel Recovered
148.35
77.75
148.5
296.7
311
297
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA Fabric-Transceiver
148.35
(MHz)
77.75
148.5
N/A
N/A
N/A
Deserializer
With Byte
74.175
148.35
(MHz)
155.5
74.25
148.5
N/A
2–41
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