DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 773

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Channels Configured in Protocol Functional Modes
Figure 3–8. Basic ×4 Functional Mode Configuration when Combining Channels
Notes to
(1) You can configure this channel in Basic (PMA Direct) single-width or double-width mode.
(2) You can configure this channel only in Basic (PMA Direct) single-width mode.
(3) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents the ×N bottom clock line.
(4) To simplify the illustration, only the transmitter side is shown. PCIe ×4 refers to PCIe with the sub protocol set to Gen1 x4 and Gen2 x4.
February 2011 Altera Corporation
Figure
3–8:
(Basic [PMA Direct] xN mdoe) (2)
4. Using the receiver side of the CMU channels depends on whether you use
5. If you use ATX PLL to generate clocks for the ×4 bonded functional mode, you can
Figure 3–8
transceiver block are used.
CMU1 PLL or CMU0 PLL to generate clocks for the bonded ×4 functional mode. If the
CMU PLL within the corresponding CMU channel is not available to perform
CDR functionality, you cannot configure it as a receiver.
use both the Transmitter and Receiver side of the CMU0 and CMU1 channels. You
must satisfy the requirements specified in number 3.
1
Figure 3–8
(PMA Direct) xN mode within the same transceiver block.
TX - Basic
For XAUI, the option to select ATX PLL is not available.
shows a configuration in which all the transmitter channels in the
CMU0 Channel
shows the combination of Basic/PCIe x4 functional mode with Basic
ATX PLL
TX2 - Basic x4/
TX3 - Basic x4/
(PMA Direct xN mode) (1)
TX1 - Basic x4/
ATX PLL
TX0 - Basic x4/
PCIe x4
PCIe x4
PCIe x4
PCIe x4
CMU1 Channel
Central Clock
Divider
x4 Clock Line (3)
xN Top Clock Line (3)
Stratix IV Device Handbook Volume 2: Transceivers
(Note 4)
xN Bottom Clock Line
3–19