DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 131

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
The mapping between the input clock pins, PLL counter outputs, and clock control
block inputs is as follows:
■
■
■
The corner PLLs (L1, L4, R1, and R4) and the corresponding clock input pins
(PLL_L1_CLK and so forth) do not support dynamic selection for the GCLK network.
The clock source selection for the GCLK and RCLK networks from the corner PLLs
(L1, L4, R1, and R4) and the corresponding clock input pins (PLL_L1_CLK and so forth)
are controlled statically using configuration bit settings in the configuration file (.sof
or .pof) generated by the Quartus II software.
Figure 5–12. RCLK Control Block
Notes to
(1) When the device is operation in user mode, you can only set the clock select signals through a configuration file (.sof
(2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input.
You can only control the clock source selection for the RCLK select block statically
using configuration bit settings in the configuration file (.sof or .pof) generated by the
Quartus II software.
You can power down the Stratix IV clock networks using both static and dynamic
approaches. When a clock network is powered down, all the logic fed by the clock
network is in off-state, thereby reducing the overall power consumption of the device.
The unused GCLK and RCLK networks are automatically powered down through
configuration bit settings in the configuration file (.sof or .pof) generated by the
Quartus II software. The dynamic clock enable or disable feature allows the internal
logic to control power-up or power-down synchronously on the GCLK and RCLK
networks, including dual-regional clock regions. This function is independent of the
PLL and is applied directly on the clock network, as shown in
Figure
inclk[0] and inclk[1]—can be fed by any of the four dedicated clock pins on the
same side of the Stratix IV device
inclk[2]—can be fed by PLL counters C0 and C2 from the two center PLLs on the
same side of the Stratix IV device
inclk[3]—can be fed by PLL counters C1 and C3 from the two center PLLs on the
same side of the Stratix IV device
or .pof) and cannot be dynamically controlled.
Figure
5–12.
5–12:
PLL Counter
Outputs
2
CLKp
Pin
Enable/
Disable
RCLK
CLKn
Pin
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Stratix IV Device Handbook Volume 1
Figure 5–11
and
5–15