DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 394

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

10–60
Table 10–16. Remote System Upgrade Status Register Contents
Stratix IV Device Handbook Volume 1
CRC (from the configuration)
nSTATUS
CORE_nCONFIG
nCONFIG
Wd
Note to
(1) Logic array reconfiguration forces the system to load the application configuration data into the Stratix IV device. This occurs after the factory
configuration specifies the appropriate application configuration page address by updating the update register.
Table
Status Register Bit
Remote System Upgrade State Machine
10–16:
1
(1)
Figure 10–27
in the figure show the bit positions within a 5-bit register.
Figure 10–27. Remote System Upgrade Status Register
The remote system upgrade control and update registers have identical bit
definitions, but serve different roles (refer to
registers can only be updated when the device is loaded with a factory configuration
image, the update register writes are controlled by the user logic; the control register
writes are controlled by the remote system upgrade state machine.
In factory configurations, the user logic sends the AnF bit (set high), the page address,
and the watchdog timer settings for the next application configuration bit to the
update register. When the logic array configuration reset (RU_nCONFIG) goes low, the
remote system upgrade state machine updates the control register with the contents
of the update register and initiates system reconfiguration from the new application
page.
To ensure successful reconfiguration between the pages, assert the RU_nCONFIG signal
for a minimum of 250 ns. This is equivalent to strobing the reconfiguration input of
the ALTREMOTE_UPDATE megafunction high for a minimum of 250 ns.
In the event of an error or reconfiguration trigger condition, the remote system
upgrade state machine directs the system to load a factory or application
configuration (page zero or page one, based on the mode and error condition) by
setting the control register accordingly.
register after such an event occurs for all possible error or trigger conditions.
and
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device logic array caused reconfiguration
Watchdog timer caused reconfiguration
Table 10–16
CRC error caused reconfiguration
nSTATUS caused reconfiguration
nCONFIG caused reconfiguration
Wd
4
Definition
nCONFIG
specify the contents of the status register. The numbers
3
Core_nCONFIG
Table 10–17
2
Table 10–14 on page
nSTATUS
lists the contents of the control
1
Dedicated Remote System Upgrade Circuitry
CRC
0
POR Reset Value
April 2011 Altera Corporation
10–57). While both
1 bit '0'
1 bit '0'
1 bit '0'
1 bit '0'
1 bit '0'