DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 522
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 522 of 1154
- Download datasheet (32Mb)
1–78
Stratix IV Device Handbook Volume 2: Transceivers
1
The rate match FIFO consists of a 20-word deep FIFO and necessary logic that controls
insertion and deletion of a skip character or ordered set, depending on the PPM
difference.
The rate match FIFO is mandatory and cannot be bypassed in the following functional
modes:
■
■
■
The rate match FIFO is optional in the following functional modes:
■
■
■
The rate match FIFO receives data from the word aligner (non-XAUI functional
modes) or deskew FIFO (XAUI functional mode) in the receiver datapath. It provides
the following status signals forwarded to the FPGA fabric:
■
■
■
■
The rate match FIFO status signals are not available in PCIe mode. These signals are
encoded on the pipestatus[2:0] signal in PCIe mode as specified in the PCIe
specification.
In PCIe mode, the rate match FIFO is capable of compensating up to ± 300 PPM (total
600 PPM) difference between the upstream transmitter and the local receiver. The
PCIe protocol requires the transmitter to send SKP ordered sets during IPGs, adhering
to rules listed in the base specification. The SKP ordered set is defined as a /K28.5/
COM symbol followed by three consecutive /K28.0/ SKP symbol groups. The PCIe
protocol requires the receiver to recognize a SKP ordered set as a /K28.5/ COM
symbol followed by one to five consecutive /K28.0/ SKP symbols.
The rate match FIFO operation is compliant to PCIe Base Specification 2.0. The rate
match operation begins after the synchronization state machine in the word aligner
indicates synchronization is acquired by driving the rx_syncstatus signal high. The
rate match FIFO looks for the SKP ordered set and deletes or inserts SKP symbols as
necessary to prevent the rate match FIFO from overflowing or under-running.
PCIe
XAUI
GIGE
Basic single-width
Basic double-width
SRIO
rx_rmfifodatainserted—indicates insertion of a skip character or ordered set
rx_rmfifodatadeleted—indicates deletion of a skip character or ordered set
rx_rmfifofull—indicates rate match FIFO full condition
rx_rmfifoempty—indicates rate match FIFO empty condition
Rate Match FIFO in PCIe Mode
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: