DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 201
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 201 of 1154
- Download datasheet (32Mb)
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT R
connected to the RUP and RDN pin; however, it is possible to achieve OCT R
other than the 25-Ω and 50-Ω resistors. Theoretically, if you need a different OCT R
value, you can change the resistance connected to the RUP and RDN pins accordingly.
Practically, the OCT R
output buffer size and granularity limitations.
The Quartus II software only allows discrete OCT R
and 60 Ω . You can select the closest discrete value of OCT R
in the Quartus II software to your system to achieve the closest timing. For example, if
you are using 20-Ω OCT R
OCT R
timing.
Table 6–8
expanded on-chip series termination with calibration of SSTL and HSTL for
impedance matching to improve signal integrity but do not use it to meet the JEDEC
standard.
Table 6–8. Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration
Range
Dynamic On-Chip Termination
Stratix IV devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks.
supported in Stratix IV devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead
of external. Termination only switches on during input operation, thus drawing less
static power.
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2
SSTL-18
SSTL-15
HSTL-18
HSTL-15
HSTL-12
S
with calibration setting in the Quartus II software to achieve the closest
I/O Standard
lists expanded OCT R
S
range that Stratix IV devices support is limited because of
S
with calibration in your system, you can select the 25-Ω
S
with calibration supported in Stratix IV devices. Use
Row I/O (Ω)
Figure 6–21
20–60
20–60
20–60
40–60
40–60
20–60
20–60
40–60
20–60
40–60
40–60
S
Expanded OCT R
to match the external resistors
S
shows the termination schemes
calibration settings of 25, 40, 50,
Stratix IV Device Handbook Volume 1
S
with calibration settings
S
Range
Column I/O (Ω)
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
20–60
S
values
6–29
S
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