DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 619

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–141. SONET/SDH OC-12 Datapath
Figure 1–142. SONET/SDH OC-48 Datapath
February 2011 Altera Corporation
tx_coreclk
rx_coreclk
tx_coreclk
rx_coreclk
FPGA
Fabric
Fabric
FPGA
FPGA Fabric-Transmitter
SONET/SDH OC-12 Datapath
Figure 1–141
mode.
SONET/SDH OC-48 Datapath
Figure 1–142
mode.
FPGA Fabric-Receiver
FPGA Fabric-Transmitter
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-12
shows the transceiver datapath when configured in SONET/SDH OC-48
tx_clkout
rx_clkout
Compensation
RX Phase
rx_clkout
Compensation
tx_clkout
FIFO
RX Phase
Compensation
FIFO
wrclk
TX Phase
Compensation
wrclk
FIFO
TX Phase
FIFO
rdclk
rdclk
Ordering
Byte
Transmitter Channel PCS
Low-Speed Parallel Clock
wrclk
Serializer
Transmitter Channel PCS
Receiver Channel PCS
Parallel Recovered Clock
Byte De-
serializer
Byte
/2
/2
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
Recovered Clock
Aligner
Word
Parallel
Aligner
Word
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Receiver Channel PMA
Transmitter Channel PMA
Serializer
Serializer
De-
Serializer
Divider
Local
Clock
Divider
Clock
Local
CDR
High-Speed
Serial Clock
CDR
High-Speed
Serial Clock
1–175