DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 339

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Configuration Features
April 2011 Altera Corporation
Power-On Reset Circuit
V
V
CCPGM
CCPD
1
1
Pins
Pins
The POR circuit keeps the entire system in reset until the power supply voltage levels
have stabilized on power-up. After power-up, the device does not release nSTATUS
until V
On power down, brown-out occurs if the V
below the threshold voltage.
In Stratix IV devices, a pin-selectable option (PORSEL) is provided that allows you to
select between the standard POR time or fast POR time. When PORSEL is driven low,
the standard POR time is 100 ms < T
When PORSEL is driven high, the fast POR time is 4 ms < T
Stratix IV devices have a power supply, V
pins and dual function pins. The supported configuration voltage is 1.8, 2.5, and 3.0 V.
Stratix IV devices do not support 1.5 V configuration.
Use the V
configuration outputs, dedicated configuration bidirectional pins, and some of the
dual functional pins that you use for configuration. With V
input buffers do not have to share power lines with the regular I/O buffer in
Stratix IV devices.
The operating voltage for the configuration input pin is independent of the I/O banks
power supply V
configuration voltage constraints on V
Stratix IV devices have a dedicated programming power supply, V
be connected to 3.0 V/2.5 V to power the I/O pre-drivers and JTAG I/O pins (TCK,
TMS, TDI, TDO, and TRST).
V
when PORSEL is low or 4 ms when PORSEL is high. If these supplies are not ramped up
within this specified time, your Stratix IV device will not configure successfully. If
your system cannot ramp up the power supplies within 100 ms or 4 ms, you must
hold nCONFIG low until all the power supplies are stable.
V
set to 3.0 V, V
2.5 V or lower, V
For more information about configuration pins power supply, refer to
Configuration Pins” on page
CCPGM
CCPD
must be greater than or equal to V
CC
and V
, V
CCPGM
CCAUX
CCPD
CCPD
pin to power all dedicated configuration inputs, dedicated
CCIO
CCPD
, V
must be powered up to 3.0 V. If the V
must ramp up from 0 V to the desired voltage level within 100 ms
CCPT
during configuration. Therefore, Stratix IV devices do not need
must be powered up to 2.5 V.
, V
CCPGM
10–39.
, and V
POR
CCIO
< 300 ms, which has a lower power-ramp rate.
CCPD
CCIO
CCPGM
.
CC
, V
are above the device’s POR trip point.
of the same bank. If V
, for all the dedicated configuration
CCAUX
, V
CCIO
CCPT
POR
CCPGM
Stratix IV Device Handbook Volume 1
of the bank is powered to
, V
< 12 ms.
CCPGM
, the configuration
CCPD
CCIO
, or V
“Device
, which must
of the bank is
CCPD
drops
10–5