DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 877

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–17. Option 1 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
February 2011 Altera Corporation
FPGA Fabric
tx_clkout[0]
Low-speed parallel clock generated by the TX0 local divider (tx_clkout[0])
High-speed serial clock generated by the CMU0 PLL
Figure 5–17
channels of a transceiver block.
■
■
Consider the following scenario:
■
■
■
Option 2 is applicable in this scenario because the design requires all four regular
transceiver channels to be reconfigured to different data rates and functional modes.
Each channel can be reconfigured to a different functional mode using the channel
and CMU PLL reconfiguration mode.
Enable this option if you want the individual transmitter channel tx_clkout
signals to provide the write clock to their respective Transmit Phase Compensation
FIFOs.
This option is typically enabled when each transceiver channel is reconfigured to a
different functional mode using channel reconfiguration.
Four regular transceiver channels configured at 3 Gbps and different functional
modes.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
You want to reconfigure each of the four regular transceiver channels to different
data rates and different functional modes.
Option 2: Use the Respective Channel Transmitter Core Clocks
shows the sharing of channel 0’s tx_clkout between all four regular
TX0 (3 Gbps/1.5 Gbps)
TX1 (3 Gbps/1.5 Gbps)
TX2 (3 Gbps/1.5 Gbps)
TX3 (3 Gbps/1.5 Gbps)
Transceiver Block
RX3
RX1
RX2
RX0
Stratix IV Device Handbook Volume 2: Transceivers
CMU1 PLL
CMU0 PLL
5–31