DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 638

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–194
Figure 1–158. Reverse Serial Pre-CDR Loopback Datapath
Stratix IV Device Handbook Volume 2: Transceivers
FPGA
Fabric
RX Phase
Compen-
sation
FIFO
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback is available as a subprotocol under Basic
functional mode. In reverse serial pre-CDR loopback, the data received through the
rx_datain port is looped back to the tx_dataout port before the receiver CDR. The
received data is also available to the FPGA logic.
channel datapath for reverse serial pre-CDR loopback mode. The active block of the
transmitter channel is only the transmitter buffer. You can change the output
differential voltage on the transmitter buffer through the ALTGX MegaWizard
Plug-In Manager. The pre-emphasis settings for the transmitter buffer cannot be
changed in this configuration.
PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in PCIe functional mode for Gen1 and
Gen2 data rates. As shown in
receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. It is then
looped back to the transmitter serializer and transmitted out through the tx_dataout
port. The received data is also available to the FPGA fabric through the rx_dataout
port. This loopback mode is compliant with the PCIe specification 2.0. To enable this
loopback mode, assert the tx_detectrxloopback port.
Ordering
Byte
Serializer
Byte
De-
Decoder
8B/10B
Figure
Transmitter Channel PCS
Receiver Channel PCS
1–159, the received serial data passes through the
Chapter 1: Transceiver Architecture in Stratix IV Devices
Aligner
Word
Figure 1–158
Serializer
Receiver Channel PMA
De-
February 2011 Altera Corporation
Transmitter Channel PMA
shows the transceiver
Serializer
Transceiver Block Architecture
Receiver
CDR
Loopback
Pre-CDR
Reverse
Serial