DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 303
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 303 of 1154
- Download datasheet (32Mb)
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Figure 8–20. Receiver Datapath in Soft-CDR Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
February 2011 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–20:
f
10
Soft-CDR Mode
The Stratix IV LVDS channel offers soft-CDR mode to support the Gigabit Ethernet
and SGMII protocols. A receiver PLL uses the local clock source for reference.
Figure 8–20
In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an
optimal DPA clock phase to sample the data. Use the selected DPA clock for bit-slip
operation and deserialization. The DPA block also forwards the selected DPA clock,
divided by the deserialization factor called rx_divfwdclk, to the FPGA fabric, along
with the deserialized data. This clock signal is put on the periphery clock (PCLK)
network. When using soft-CDR mode, the rx_reset port must not be asserted after
the rx_dpa_lock is asserted because the DPA will continuously choose new phase
taps from the PLL to track parts per million (PPM) differences between the reference
clock and incoming data.
For more information about periphery clock networks, refer to the
PLLs in Stratix IV Devices
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the soft-CDR mode datapath.
IOE
2
Left/Right PLL
3
DOUT DIN
Clock Mux
Bit Slip
(LVDS_LOAD_EN,
LVDS_diffioclk,
chapter.
(Note
rx_outclk)
diffioclk
1), (2),
rx_inclock
(3)
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Stratix IV Device Handbook Volume 1
Retimed
Data
DPA Clock
DPA Circuitry
Clock Networks and
DIN
+
LVDS Clock Domain
DPA Clock Domain
rx_in
8–25
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