DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 455

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
February 2011 Altera Corporation
Figure 1–6
the EP4S40G5H40 Stratix IV GT devices.
Figure 1–6. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S40G5H40
Stratix IV GT Devices
Note to
(1) If you are using the PCIe hard IP block, the EP4S40G2F40 device is not able to migrate to the EP4S40G5H40 device.
Figure
EP4S40G5H40
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
shows the transceiver channel, PLL, and PCIe hard IP block locations for
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
CMU Channel 1
CMU Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
1–6:
8G Channel 1
8G Channel 0
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
ATX PLL (6G)
8G Channel 3
8G Channel 2
(Note 1)
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
10G Channel 3
10G Channel 2
10G Channel 1
10G Channel 0
10G Channel 3
10G Channel 2
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
8G Channel 1
8G Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
8G Channel 1
8G Channel 0
8G Channel 3
8G Channel 2
ATX PLL (6G)
1–11