DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 146

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–30
Stratix IV Device Handbook Volume 1
1
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock-output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the delay introduced by the GCLK or RCLK network is fully
compensated.
relationship in normal mode.
Figure 5–25. Phase Relationship Between the PLL Clocks in Normal Mode
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
Zero-Delay Buffer (ZDB) Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin
for zero-delay through the device. When using this mode, you must use the same I/O
standard on the input clocks and output clocks to guarantee clock alignment at the
input and output pins. ZDB mode is supported on all Stratix IV PLLs.
When using Stratix IV PLLs in ZDB mode, along with single-ended I/O standards, to
ensure phase alignment between the CLK pin and the external clock output (CLKOUT)
pin, you must instantiate a bi-directional I/O pin in the design to serve as the
feedback path connecting the FBOUT and FBIN ports of the PLL. The PLL uses this
bi-directional I/O pin to mimic, and compensate for, the output delay from the clock
output port of the PLL to the external clock output pin.
in Stratix IV PLLs. When using ZDB mode, you cannot use differential I/O standards
on the PLL clock input or output pins.
The bi-directional I/O pin that you instantiate in your design must always be
assigned a single-ended I/O standard.
Figure
Dedicated PLL Clock Outputs (1)
5–25:
Figure 5–25
Register Clock Port
PLL Clock at the
PLL Reference
Clock at the
Input Pin
shows an example waveform of the PLL clocks’ phase
Phase Aligned
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Figure 5–26
February 2011 Altera Corporation
PLLs in Stratix IV Devices
shows ZDB mode