DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 55

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Document Revision History
Document Revision History
Table 2–1. Document Revision History
February 2011 Altera Corporation
February 2011
November 2009
June 2009
March 2009
November 2008
May 2008
Date
LAB Power Management Techniques
f
Version
The following techniques are used to manage static and dynamic power consumption
within the LAB:
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For more information about implementing static and dynamic power consumption
within the LAB, refer to the
Handbook.
Table 2–1
3.0
2.0
3.1
2.2
2.1
1.0
To save AC power, the Quartus II software forces all adder inputs low when ALM
adders are not in use.
Stratix IV LABs operate in high-performance mode or low-power mode. The
Quartus II software automatically chooses the appropriate mode for the LAB,
based on the design, to optimize speed versus leakage trade-offs.
Clocks represent a significant portion of dynamic power consumption due to their
high switching activity and long paths. The LAB clock that distributes a clock
signal to registers within an LAB is a significant contributor to overall clock power
consumption. Each LAB’s clock and clock enable signal are linked. For example, a
combinational ALUT or register in a particular LAB using the labclk1 signal also
uses the labclkena1 signal. To disable LAB-wide clock power consumption
without disabling the entire clock tree, use LAB-wide clock enable to gate the
LAB-wide clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within the LAB that share a
common clock and clock enable are controlled by a shared, gated clock. To take
advantage of these clock enables, use a clock-enable construct in your HDL code
for the registered logic.
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Removed “Referenced Documents” section.
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Initial release.
Updated
Applied new template.
Minor text edits.
Updated graphics.
Minor text edits.
Removed the Conclusion section.
Added introductory sentences to improve search ability.
Minor text edits.
Updated Figure 2–6.
Made minor editorial changes.
lists the revision history for this chapter.
Figure
2–6.
Power Optimization
Changes
chapter in volume 2 of the Quartus II
Stratix IV Device Handbook Volume 1
2–19