DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 873

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–15. Reconfiguring the CMU0 PLL
February 2011 Altera Corporation
refclk0
refclk1
156.25 MHz
Unused Connections
125 MHz
Active Connections
5. Provide the starting channel number in the Modes screen. For more information,
6. Provide the logical reference index of the CMU PLL in the What is the PLL logical
7. Provide the identification of the input reference clock used by the CMU PLL in the
8. Set up the Clocking/Interface options. For more information, refer to
9. Set up the Channel Interface options. For more information, refer to
To reconfigure the CMU PLL during run time, you need the flexibility to select one of
the two CMU PLLs of a transceiver block.
Consider that the transceiver channel is listening to CMU0 PLL and that you want to
reconfigure CMU0 PLL, as shown in
refer to
reference index? option in the corresponding PLL screen. For more information,
refer to
corresponding PLL screens.
“Clocking/Interface Options” on page
Fabric-Transceiver Channel Interface Selection” on page
Using the Alternate CMU Transmitter PLL
“Logical Channel Addressing” on page
“Selecting the Logical Reference Index of the CMU PLL” on page
clock
mux
clock
mux
logical_tx_pll value = 0
Alternate PLL
CMU Channels
6.25 Gbps
CMU0 PLL
2.5 Gbps
CMU1 PLL
logical_tx_pll value = 1
Figure
Main PLL
1
0
5–15.
5–30.
Logical
TX PLL
select
clock
mux
Stratix IV Device Handbook Volume 2: Transceivers
5–5.
Full Duplex Transceiver Channel
DIVIDER
LOCAL
6.25 Gbps
RX CHANNEL
RX CDR
TX CHANNEL
5–36.
TX PMA + TX PCS
RX PMA + RX PCS
6.25 Gbps
6.25 Gbps
“FPGA
5–29.
5–27