DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 520
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 520 of 1154
- Download datasheet (32Mb)
1–76
Figure 1–58. Deskew FIFO—Lane Skew at the Receiver Input
Stratix IV Device Handbook Volume 2: Transceivers
Lane 0
1
Lane 2
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Deskew circuitry performs the deskew operation by the XAUI functional mode.
Deskew circuitry consists of:
■
■
Deskew circuitry is only available in XAUI mode.
The deskew FIFO in each channel receives data from its word aligner. The deskew
operation begins only after link synchronization is achieved on all four channels as
indicated by a high level on the rx_syncstatus signal from the word aligner in each
channel. Until the first /A/ code group is received, the deskew FIFO read and write
pointers in each channel are not incremented. After the first /A/ code group is
received, the write pointer starts incrementing for each word received but the read
pointer is frozen. If the /A/ code group is received on each of the four channels
within 10 recovered clock cycles of each other, the read pointer for all four deskew
FIFOs is released simultaneously, aligning all four channels.
Figure 1–58
/A/ code group to align the channels.
After alignment of the first ||A|| column, if three additional aligned ||A||
columns are observed at the output of the deskew FIFOs of the four channels, the
rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at the
output of the deskew FIFOs in all four channels with no aligned ||A|| columns in
between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel
alignment.
Lane 0
Lane 1
Lane 2
Lane 3
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A 16-word deep deskew FIFO in each of the four channels
Control logic in the CMU0 channel of the transceiver block that controls the deskew
FIFO write and read operations in each channel
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shows lane skew at the receiver input and how the deskew FIFO uses the
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Chapter 1: Transceiver Architecture in Stratix IV Devices
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February 2011 Altera Corporation
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Transceiver Block Architecture
Lane Skew at
Receiver Input
Lanes are
Deskewed by
Lining up
the "Align"/A/,
Code Groups
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