DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 728

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–56
Stratix IV Device Handbook Volume 2: Transceivers
Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write
Clock
The Quartus II software uses a single tx_clkout signal to clock the transmitter phase
compensation FIFO write port of all identical channels within a transceiver block.
This results in one global and/or regional clock resource being used for each group of
identical channels within a transceiver block.
For identical channels located across the transceiver blocks, the Quartus II software
does not use a single tx_clkout signal to clock the write port of the transmitter phase
compensation FIFOs for all channels. It uses one tx_clkout signal for each group of
identical channels per transceiver block. This results in higher global and regional
clock resource usage.
Example 4: Sixteen Identical Channels Across Four Transceiver Blocks
Figure 2–31
blocks. The Quartus II software uses tx_clkout from Channel 0 in each transceiver
block to clock the write port of the transmitter phase compensation FIFO in all four
channels in that transceiver block. This results in four global and/or regional clock
resources being used, one for each transceiver block.
shows 16 identical transmitter channels located across four transceiver
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation