DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 132
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 132 of 1154
- Download datasheet (32Mb)
5–16
Stratix IV Device Handbook Volume 1
f
1
You can set the input clock sources and the clkena signals for the GCLK and RCLK
network multiplexers through the Quartus II software using the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
using the ALTCLKCTRL megafunction.
clock control block.
When using the ALTCLKCTRL megafunction to implement dynamic clock source
selection, the inputs from the clock pins feed the inclk[0..1] ports of the multiplexer,
while the PLL outputs feed the inclk[2..3] ports. You can choose from among these
inputs using the CLKSELECT[1..0] signal.
For more information, refer to the
User
Figure 5–13. Stratix IV External PLL Output Clock Control Block
Notes to
(1) When the device is operation in user mode, you can only set the clock select signals through a configuration file (.sof
(2) The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin’s IOE. The PLL_<#>_CLKOUT
or .pof) and cannot be dynamically controlled.
pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control
block.
Guide.
Figure
5–13:
IOE
Internal
Logic
(2)
PLL_<#>_CLKOUT pin
7 or 10
Clock Control Block (ALTCLKCTRL) Megafunction
PLL Counter
Outputs
Enable/
Disable
Figure 5–13
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Internal
Static Clock
Select (1)
Logic
Static Clock Select
shows the external PLL output
(1)
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
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