DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 122

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–6
Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices)
Stratix IV Device Handbook Volume 1
Periphery Clock Networks
PCLK networks shown in
individual clock networks driven from the periphery of the Stratix IV device. Clock
outputs from the dynamic phase aligner (DPA) block, programmable logic device
(PLD)-transceiver interface clocks, horizontal I/O pins, and internal logic can drive
the PCLK networks.
PCLKs have higher skew when compared with GCLK and RCLK networks. You can
use PCLKs for general purpose routing to drive signals into and out of the Stratix IV
device.
Legal clock sources for PCLK networks are clock outputs from the DPA block,
PLD-transceiver interface clocks, horizontal I/O pins, and internal logic.
CLK[0..3]
L2
PCLK[14..27]
PCLK[0..13]
Figure 5–5
CLK[12..15]
Q1
Q4
CLK[4..7]
T1
B1
Q2
Q3
through
PCLK[28..41]
PCLK[42..56]
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Figure 5–8 on page 5–8
R2
CLK[8..11]
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation
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