DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 351

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Active Serial Configuration (Serial Configuration Devices)
April 2011 Altera Corporation
1
Serial configuration devices have a four-pin interface—serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This
four-pin interface connects to Stratix IV device pins, as shown in
Figure 10–6. Single Device Fast AS Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) Stratix IV devices use the ASDO-to-ASDI path to control the configuration device.
You can power the EPCS serial configuration device with 3.0 V when you configure
the Stratix IV FPGA using Active Serial (AS) configuration mode. This is feasible
because the power supply to the EPCS device ranges between 2.7 V and 3.6 V. You do
not need a dedicated 3.3 V power supply to power the EPCS device. The EPCS device
and the VCCPGM pins on the Stratix IV device may share the same 3.0 V power supply.
After power-up, the Stratix IV devices go through a POR. The POR delay depends on
the PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T
4 ms < T
low, and tri-states all user I/O pins. After the device successfully exits POR, all the
user I/O pins continue to be tri-stated. If nIO_pullup is driven low during power-up
and configuration, the user I/O pins and dual-purpose I/O pins will have weak
pull-up resistors, which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages—reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset. After POR, the
Stratix IV device releases nSTATUS, which is pulled high by an external 10-kΩ pull-up
resistor and enters configuration mode.
To begin configuration, power the V
banks where the configuration pins reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix IV device controls the entire
configuration cycle and provides timing for the serial interface. Stratix IV devices use
an internal oscillator to generate DCLK. Using the MSEL[] pins, you can select to use a
40 MHz oscillator.
Figure
POR
Serial Configuration
POR
< 12 ms. During POR, the device resets, holds nSTATUS and CONF_DONE
10–6:
< 300 ms. When PORSEL is driven high, the fast POR time is
Device
DATA
DCLK
ASDI
nCS
V
CCPGM (1)
CCPGM
10
at a 3.0-V supply.
kΩ
V
CCPGM (1)
(2)
CC
10
, V
kΩ
CCIO
V
GND
CCPGM (1)
, V
10
kΩ
CCPGM
nCONFIG
nSTATUS
CONF_DONE
nCE
DATA0
DCLK
nCSO
ASDO
Stratix IV Device
, and V
Stratix IV Device Handbook Volume 1
CCPD
MSEL2
MSEL1
MSEL0
nCEO
Figure
voltages (for the
V
CCPGM
10–6.
N.C.
GND
10–17