DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 64

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–8
Figure 3–6. ECC Block Diagram of the M144K Block
Memory Modes
Stratix IV Device Handbook Volume 1
Data Input
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c
Figure 3–6
Stratix IV TriMatrix memory blocks allow you to implement fully synchronous SRAM
memory in multiple modes of operation. M9K and M144K blocks do not support
asynchronous memory (unregistered inputs). MLABs support asynchronous
(flow-through) read operations.
Depending on which TriMatrix memory block you target, you can use the following:
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■
■
■
■
■
When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or
hold-time on any of the memory block input registers. This applies to both read and
write operations.
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“Single-Port RAM Mode” on page 3–9
“Simple Dual-Port Mode” on page 3–10
“True Dual-Port Mode” on page 3–13
“Shift-Register Mode” on page 3–15
“ROM Mode” on page 3–16
“FIFO Mode” on page 3–16
SECDED
Encoder
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shows a diagram of the ECC block of the M144K block.
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72
RAM
Array
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
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Data Output
Correction
Error
Block
SECDED
Encoder
8
64
Locator
Error
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February 2011 Altera Corporation
8
8
Comparator
8
Status Flags
Memory Modes
Generator
Flag
3