DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 688

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–16
Figure 2–10. Legal FPGA Fabric-Transceiver PLL Cascading Configuration
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 0
Channel 2
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 3
Channel 0
Channel 0
Channel 3
Channel 2
Channel 1
Channel 1
ATX PLL L1 (6G)
ATX PLL L0 (6G)
CMU1
CMU1
CMU0
CMU0
CMU1
CMU1
CMU0
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Case 2: use PLL_R1 to provide the input reference clock to the receiver CDRs in
channel 2 and channel 3 (shown in BLUE) and use PLL_R4 to provide the input
reference clock to the CMU0 PLL (shown in GREEN) in transceiver block GXBR1.
Figure 2–10
legal as there is no crossover of the cascade clock paths on the PLL cascade network.
Cascade
Network
PLL
shows that this FPGA fabric-Transceiver PLL cascading configuration is
PLL_L3
PLL_L2
PLL_L4
PLL_L1
EP4SGX530NF45
PLL_R3
PLL_R2
PLL_R1
PLL_R4
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Cascade
Network
PLL
February 2011 Altera Corporation
Transceiver Block GXBR0
Transceiver Block GXBR2
Transceiver Block GXBR2
Transceiver Block GXBR1
ATX PLL R1 (6G)
ATX PLL R0 (6G)
CMU1
CMU1
CMU1
CMU1
CDR
CMU0
CDR
CMU0
CDR
CMU0
CDR
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Channel 2
Channel 2
Channel 1
Channel 0
Channel 3
Channel 1
Channel 0
Channel 3
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 0
Channel 1