DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 760
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 760 of 1154
- Download datasheet (32Mb)
3–6
Stratix IV Device Handbook Volume 2: Transceivers
Each channel instance can have a different local divider setting. This is a useful option
when you intend to run each channel within the transceiver block at different data
rates that are derived from the same base data rate using the local divider values /1,
/2, and /4.
Example 1
Consider an example design with four instances of a Receiver and Transmitter
configuration in the same transceiver block at various serial data rates. Assume that
each instance contains a channel and is driven from the same clock source and has the
same CMU PLL bandwidth settings.
Table 3–2. Configuration for Example 1
For Example 1, you can share a single CMU PLL for all four channels because:
■
■
To enable the Quartus II software to share a single CMU PLL for all four channels, set
the values listed in
Plug-In Manager.
Table 3–3. ALTGX MegaWizard Plug-In Manager Settings for Example 1
One CMU PLL can be configured to run at 4.25 Gbps.
Each channel can divide the CMU PLL clock output using the local divider and
achieve the required data rates of 4.25 Gbps, 2.125 Gbps, and 1.0625 Gbps. Because
each receiver channel has a dedicated CDR, the receiver side in each instance can
be set up for these three data rates without any restrictions.
Instance Name
User-Created
Instance
inst0
inst1
inst2
inst3
inst0
inst1
inst2
Example 1
Table 3–3
shows this design configuration.
Number of Channels
What is the effective data rate?
Specify base data rate
What is the effective data rate?
Specify base data rate
What is the effective data rate?
Specify base data rate
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
in the General screen of the ALTGX MegaWizard
1
1
1
1
General Screen Option
ALTGX MegaWizard Plug-In Manager Settings
Table 3–2
lists the configuration for Example 1.
Configuration
Receiver and
Receiver and
Receiver and
Receiver and
Transmitter
Transmitter
Transmitter
Transmitter
February 2011 Altera Corporation
Effective Data Rate
Setting (Gbps)
4.25
4.25
4.25
1.0625
(Gbps)
1.0625
Sharing CMU PLLs
2.125
2.125
4.25
4.25
4.25
(1)
(1)
(1)
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