DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 774

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–20
Stratix IV Device Handbook Volume 2: Transceivers
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1
Bonded x8 Functional Mode
Bonded ×8 functional mode is similar to bonded ×4 functional mode except that the
controls are shared from the physical channel 0 of the master transceiver block. The
master is the lower of the two adjacent transceiver blocks selected for the ×8
configuration. Therefore, when you an create an instance in this mode, you must
assign the logical transmit channel 0 (tx_dataout[0] in the instance to the physical
channel location 0 in the master transceiver block.
There are specific transceiver blocks that can be paired as master-slave in the ×8
configuration.
The master is the adjacent lower transceiver block. For more information about
location requirements, refer to the “Bonded Channel Configurations” section of the
Transceiver Clocking in Stratix IV Devices
In Basic ×8 functional mode, you can select the number of channels to be less than 8
by setting the What is the number of channels? option on the General screen. In this
instance, you can use the remaining transmitter channels only in Basic (PMA Direct)
×1 or ×N mode. In PCIe Gen1 ×8 and Gen2 ×8 functional modes, the number of
regular channels used is always 8.
The number of remaining transmitter channels (CMU channels or regular channels) in
the two transceiver blocks available for use in Basic (PMA Direct) ×1 or ×N mode
depends on whether the ×8 functional mode uses CMU PLL or ATX PLL, as described
below.
If PCIe functional mode uses the PCIe hard IP block, the combination requirements
are different. For more information, refer to
hard IP Block with Other Channels” on page
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
chapter.
Combining Channels Configured in Protocol Functional Modes
“Combining Channels Using the PCIe
3–24.
February 2011 Altera Corporation